Modular Hardware-in-the-Loop
Test Platform.
Drop your DUT onto the matching platform adapter, point the IV&V framework at it, and run a full regression suite before lunch. Built on Kria K26 — same Yocto BSP, same engineers, same evidence trail.
HIL-Bench · HIL-Rack · HIL-Cert · AMD Kria K26 · Yocto Linux · FreeRTOS
First test in minutes, not weeks. On real silicon.
No vendor lock-in. No proprietary RTOS. No unfamiliar toolchain. The SoCcentric HIL is built on the same Kria K26 SoM, the same Yocto BSP, and the same IV&V framework already running in your program. Your engineers already know the stack.
The HIL is the seventh SoCcentric platform — a slot-based chassis with a fixed brain card, swappable platform adapter boards, and an extension-card catalog. Every interface beyond the common-denominator base is a card you choose.
Your DUT runs its real firmware against real electrical signals. No SPICE model, no emulation layer, no "it works in sim" surprises on first board-bring-up.
The HIL is a peripheral of the IV&V platform, not a separate tool. Test orchestration, evidence database, and Web UI carry forward unchanged.
Every measurement channel is calibrated and traceable. Certification mode — with signed, timestamped, requirement-mapped reports — is standard, not an upgrade.
One chassis. Any DUT. Every signal.
Three layers: the K26 brain card (APU running Yocto + IV&V, RPU running FreeRTOS watchdog, PL hosting FPGA I/O soft-IP), the slot backplane (six card slots sharing a high-speed HIL-Bus), and the platform adapter (DUT-specific connector and power conditioning). Swap the adapter to change the DUT. Swap the extension cards to change the interfaces.
APU runs Yocto + IV&V framework; RPU runs FreeRTOS watchdog; PL hosts FPGA I/O and timing soft-IP
DUT-specific PCB — connector, power conditioning, and signal translation. One adapter per SoCcentric platform
Slot cards for DIO, AIO, CAN/CAN-FD, Ethernet bus, motor/encoder, and more — chosen for each program
The HIL connects to the IV&V server over gRPC and PTP — same test orchestration, same evidence database, same Web UI
Three chassis tiers. One architecture.
HIL-Bench for desk-side bring-up, HIL-Rack for overnight CI regression, HIL-Cert for certification-grade evidence. Each tier shares the same K26 brain card, the same Yocto BSP, and the same IV&V integration. Fault injection — GPIO stuck faults, CAN bit errors, brown-out sweeps — runs as a campaign across all three tiers.
HIL-Bench
TIER 01 / BENCHFour-slot desktop chassis for firmware bring-up at the engineer's desk. Plug in the DUT, open a browser to the Web UI, run a smoke test, and have results in under five minutes from power-on.
HIL-Rack
TIER 02 / RACKSix-slot 2U rackmount chassis for headless CI regression. Triggered by a Git push, results posted as JUnit XML to the IV&V dashboard. Failed runs include captured waveforms, bus traces, and console logs as artifacts.
HIL-Cert
TIER 03 / CERTEight-slot 3U chassis with calibrated measurement channels, PTP time sync, and signed evidence output. The certification regression pack produces a traceable report mapping each test to its requirement, including calibration provenance for every measurement channel.
Fault Injection
MODE 04 / FAULTDeterministic fault injection campaign across all tiers. Stuck-high GPIO, CAN bit errors mid-frame, brown-out at varying voltages, sensor signal clipping — each fault scripted, injected, and scored against expected DUT behavior.
Six card slots. Every interface your DUT needs.
The HIL-Bus backplane connects the K26 brain card to up to six slot cards. The base set covers the common-denominator interfaces. Add extension cards for the protocols and signals your specific program requires. One chassis, any DUT class.
Five test disciplines. Hardware-up.
From pin-level GPIO validation to rest-of-bus emulation, fault injection to plant-in-the-loop motor control. Every discipline produces the same calibrated, traceable evidence trail — ready for your IV&V dashboard and certification submission.
Firmware bring-up
GPIO walk, peripheral smoke test, console capture, and boot-time health check. Engineer plugs in the DUT, opens the Web UI, and has a pass/fail result in under five minutes. Every signal state logged with FPGA edge timestamps.
Bus emulation
CAN-FD, EtherCAT, PROFINET, and SPI bus emulation with up to 12 virtual nodes per channel. The DUT believes it is in the real vehicle, machine, or network. Bus traffic captured with Wireshark-compatible pcap for post-run analysis.
Fault injection
Stuck-high GPIO, CAN bit errors mid-frame, brown-out at programmable voltages, sensor signal clipping. Each fault injected deterministically by the FPGA, DUT response captured, scored against expected behavior, and persisted in the evidence database.
Synthetic sensor injection
Programmable analog waveforms on calibrated DAC channels for ADC validation and sensor emulation. IMU, pressure, temperature, and encoder signals synthesized to spec. Deterministic timestamping aligned to the rest of the simulated environment.
Certification evidence
Calibration provenance on every measurement channel. Signed, timestamped, requirement-mapped test reports. Append-only evidence database — every run, every parameter, every result. ISO 26262, DO-178C, IEC 62304, and IEC 61508 artifact shapes supported.
Nine industries. Purpose-built HIL test rigs.
Motor controller ECU with CAN-FD rest-of-bus emulation — ASIL-B.
12 virtual CAN-FD nodes emulated with fault injection and a 25–95 °C thermal sweep; bus error rates and DUT response times mapped to ASIL-B linkage.
UAV flight controller GPIO and UART — DO-254 fault injection.
GPIO walk, UART telemetry quality, and stuck-line faults injected at each simulated altitude step; all run records retained for structural-coverage review.
Tactical radio SBC — MIL-STD-810 with active fault injection.
UART parity errors, power brown-outs, and GPIO fault states injected under combined thermal and vibration profiles for tamper-evident programme records.
Safety PLC DIO and Ethernet — IEC 61508 SIL-2 closed-loop.
Field devices emulated, communication faults injected, fault-response time and recovery latency measured and captured for SIL-2 functional-safety review.
AGV motor controller plant-in-the-loop — IEC 61508 SIL-2.
Real-time motor plant model on K26 brain card with encoder emulation on AIO, peak-load fault injection, and integrity evidence captured per scenario.
EV BMS full cell pack and fault emulation — ASIL-D.
96 cell channels emulated on calibrated AIO cards; overvoltage and thermal-runaway faults injected with DUT fault-response latency mapped to ASIL-D requirements.
Train control unit vital I/O and network — EN 50128 SIL-3.
Trackside sensor network emulated; communication failures and power-cycle events injected with fault-response times captured for safety authority submission.
Satellite payload controller power-rail fault injection — ECSS.
Brown-out, over-voltage, and latch-up events injected on calibrated power channels; recovery timing and state-machine integrity captured across temperature.
Smart grid edge controller load step and fault injection — IEC 62443.
Modbus/RTU field devices emulated; protocol errors and power transients injected with DUT response measured under worst-case disturbance scenarios.
Every channel calibrated. Every run traceable.
Calibration provenance on every measurement channel. Signed, timestamped, requirement-mapped test reports. Append-only evidence database — every run, every parameter, every result. The same IV&V evidence framework, with HIL hardware provenance added.
Engineering questions, answered straight.
Connect
Ready to see hardware-in-the-loop on your DUT?
Get in touch with our engineers. Tell us your platform, your DUT, and what you need to test. We will scope the right chassis tier and adapter. Already running IV&V? The HIL connects to the same server — no new tooling required.
NO SALES PRESSURE. NO PRICING WALL. ENGINEERS TALKING TO ENGINEERS.